Category Archives: bit error rate equation

Flash Temperature Testing and Modeling

Temperature Testing

This an expanded version of the temperature modeling section from my Flash Memory Summit 2014 Tutorial T1.

An accurate temperature model is vital for flash devices as most vendors rely on accelerate temperature testing to verify retention capabilities. I tested flash at the SSD level as this is how the devices are integrated in to storage systems. All tests were performed using devices supporting a host-managed interface. Continue reading

Series SDD 5: The error rate surface for MLC NAND flash

Update July 2014: modified bit-error equation

I have modified the MLC equation based on examination of further data.

Expected behavior of the  MLC error rate surface

NAND flash has rather complex bit error rate behavior compared with magnetic recording. In the case of hard disks, the bit error rate behavior tends to be a constant, without strong dependence on other factors. For a given bit, the error rate doesn’t depend on the number of write cycles or the age of the data. Unfortunately, the same can’t be said for flash. Flash has a complex multi-dimensional error rate surface. Continue reading