Series SSD: 7. Bit error rate – cycling data (endurance)

Program-Erase Cycling data (endurance)

Authors note: I am working diligently to get all the data together into a consumable format. Since this is turning out to be a time consuming process given the volume of data, I will be updating this post as I get the data ready. Once I get the data posted, then I’ll get back to the analysis.

Update March 2013

I finally got all the cycling data for the 3xnm class devices collated so you can preview it while I write up the analysis. As you can see, there is quite a bit of data. I have posted the data in high-res images galleries so you can see the details.

The Cycling Test

As described in chapter 6, the cycling tests are designed to rapidly reach a given Program-erase cycle count, at which point data aging tests are performed. Unless noted, the erase-to-write dwell time is 250ms if the data isn’t going to be read, and 360ms if it will be read. The write-to-read dwell time is 500ms.

The data is presented as raw bit error rate vs. program-erase cycle count.

70C raw cycling data

The following gallery shows the raw cycling data at 70C for a set of 3xnm devices. Cycle measurements here were taken out to 14k cycles. These device have a specified 3k program erase cycle limit, a 70C max operating temperature and 1 year retention.

The astute observer may have noticed some non-uniformity in the bit error noise characteristics. Namely, there are spikes in the bit error rate. I have decided to call these error fountains. I plan to devote a chapter to this phenomenon.

60C raw cycling data

The following gallery shows the raw cycling data at 60C for a set of 3xnm devices. Cycle measurements here were taken out to 20k cycles here. These device have a specified 3k program erase cycle limit, a 70C max operating temperature and 1 year retention.

I have run some of these tests to higher cycling counts than the 70C data.Again, the bit error noise characteristics aren’t always uniform. Some of the test parameters were adjusted in some of these tests. I’ll point these out where they show changes in behavior.

40C raw cycling data

The following gallery shows the raw cycling data at 40C for a set of 3xnm devices. Cycle measurements here were taken out to 20k cycles here. These device have a specified 3k program erase cycle limit, a 70C max operating temperature and 1 year retention.

I have run some of these tests to higher cycling counts than the 70C data. Again, the bit error noise characteristics aren’t always uniform. Some of the test parameters were adjusted in some of these tests. I’ll point these out where they show changes in behavior.

30C raw cycling data

The following gallery shows the raw cycling data at 30C (well, 28C if you want to get technical) for a set of 3xnm devices. Cycle measurements here were taken out to 14k cycles here. These device have a specified 3k program erase cycle limit, a 70C max operating temperature and 1 year retention.

Again, the bit error noise characteristics aren’t always uniform. Some of the test parameters were adjusted in some of these tests. I’ll point these out where they show changes in behavior.

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